Reinforcement Learning Framework for Efficient Placement and Routing in VLSI

As integrated circuit design advances into deep sub-micron technologies and multi-billion-transistor systems, the physical design (PD) stage has emerged as a critical bottleneck in achieving timely design closure. Traditional PD methodologies rely heavily on iterative, rule-based Electronic Design Automation (EDA) flows, where placement, clock tree synthesis (CTS), and routing are repeatedly adjusted to fix setup and hold violations, clock skew, and routing congestion. This reactive approach often requires 10 to 50 iterations, leading to increased turnaround time, higher engineering effort, and uncertain convergence. This paper explores Artificial Intelligence (AI) and Machine Learning (ML) driven automation techniques to address four key PD challenges: timing violations, routing congestion, clock uncertainty, and excessive iteration cycles. Techniques such as supervised learning, Graph Neural Networks (GNNs), and Reinforcement Learning (RL) are integrated across different PD stages—from netlist analysis to routing—to enable predictive and proactive optimization. By leveraging historical design data and graph-based feature extraction, these models are embedded within commercial EDA tools to improve decision-making. Conceptual evaluation on benchmark circuits indicates that AI-driven flows can reduce iteration counts to 4–6 and accelerate PD stages by 40–67%, offering a scalable solution for faster and more reliable design closure.