Design and Implementation of a Lightweight PHOTON Hash Function on FPGA platform

Devices with limited resources, such RFID systems, embedded platforms, and Internet of Things nodes, must be secured using lightweight cryptographic primitives. For low-area FPGA deployments, traditional hash functions and integrated encryption-signature techniques are inappropriate due to their substantial computational and hardware overhead. In this study, we design and implement the PHOTON-80/20/16 lightweight hash function using Verilog-HDL on an Artix-7 FPGA. The architecture operates on a 5x5 state matrix over GF (2⁴) and is based on the sponge construction with an AES-like substitution-permutation network. In order to effectively balance throughput and hardware utilization, a round-based iterative architecture with a 100-bit datapath is used. For the SubCells and MixColumns transformations, LUT-based optimization is used to minimize computing complexity. At a maximum frequency of 347.403 MHz, the suggested implementation uses 125 slices and achieves a throughput of 2316.02 Mbps with a latency of 15 clock cycles. A comparison with current PHOTON-80/20/16 architectures shows better throughput-to-area efficiency. The outcomes validate that the suggested design offers a dependable, low-power hashing solution appropriate for embedded security and secure authentication based on FPGA.