N x N Memristive Crossbar Array with LIF Neuron model using VHDL

Memristor crossbar arrays as a form of in-memory computing offers advantages in terms of density, nonvolatility and compatibility with CMOS technology. One challenge, however, is that traditional simulation methods such as HSPICE, while accurate, cannot run large-scale design verification operations in a reasonable timeframe. To address this challenge, we present a fast VHDL-based design and verification framework to support the design of memristor crossbar systems under MAGIC and FBLC logic families. This tool provides functional validation and energy, delay, timing and area overhead measurements. Performance results show that, compared to traditional simulators like HSPICE, our framework provides up to 153× speed increase in simulation execution time, with only 6% to 10% error rate for energy and delay estimates. Moreover, the framework was successfully explored through a simple 1-bit full adder block and allows for early analyses of memristor-based in-memory computing hardware implementations.