Performance Evaluation of Multiplier Architectures for FFT Processor

The performance investigation of various multiplier architectures has been proposed for FFT Processor design. In this article, six different multiplier designs— Booth Multiplier, Array Multiplier, Wallace Tree, Dadda Multiplier, Baugh-Wooley as well as Vedic Urdhva Tiryagbhyam (UT) multiplier, are systematically compared with respect to delay, frequency as well as power with the hardware silicon area. The Virtex6 XC6VCX75T FF484 FPGA board is used to implement numerous multiplier architectures for an FFT processor. The synthesis results show that the Urdhva Tiryagbhyam multiplier is the most suitable choice to achieve an optimized FFT Processor for a OFDM transceiver system. As compared with typical multiplier architectures, the Urdhva Tiryagbhyam vedic multiplier achieved lower hardware area as well as delay. The results of this article are useful for finding out the best and most effective multiplier topologies for implementing FFT processors.