High Gain Low Noise Figure LNA for sub-6 GHz spectrum

Abstract: In this paper, a Low Noise Amplifier (LNA) is proposed with the objective of achieving a low noise figure, moderate gain, and low power consumption It comprises two stages: the first is a Cascode configuration utilizing a pair of NMOS and PMOS transistors connected to share a common biasing current, thereby reducing power consumption. The equivalent transconductance of this stage is the product of the individual transconductances, resulting in increased gain. The output of the first stage feeds into a body-biased common-source stage, which enhances both gain and linearity. The frequency range from 2.5 GHz to 8 GHz was utilized for simulation purposes, conducted using Cadence software. The simulation results indicate a forward voltage gain of 19.8 dB and an input reflection coefficient (S11) less than -10 dB at 5 GHz. The proposed Low Noise Amplifier (LNA) consumes 1.9 mW of power at a supply voltage of 1.5 V across the entire frequency band