Design And Implementation of Spiking Neural Network Using MTJ Model

Advanced non-volatile memory systems demand device models that simultaneously provide physical accuracy and computational efficiency for circuit-level integration. Spin-Transfer Torque Magnetic Tunnel Junctions (STT-MTJs) have emerged as promising building blocks for next-generation memory and in-memory computing architectures due to their non-volatility, high endurance, low standby power, and CMOS compatibility. This paper presents the design and implementation of a physics-based Verilog-A compact model for STT-MTJ devices, capable of accurately capturing magnetization dynamics, tunneling magnetoresistance behavior, and current-induced switching characteristics. The proposed model is integrated with CMOS circuitry to realize a 1T–1MTJ memory cell, enabling detailed analysis of read and write operations under transient conditions. Furthermore, the design is extended to a 2×2 MTJ-based crossbar array to investigate array-level behavior, cell selectivity, and interaction effects. Simulations are performed using Cadence Spectre with 180-nm CMOS technology, demonstrating reliable magnetization switching, stable non-volatile data retention, and consistent electrical characteristics across different operating conditions. The results validate the effectiveness of the developed model as a compact and scalable framework for STT-MRAM design and emerging spintronic in-memory computing applications.