Power Modelling of FPGA Implementations at System Level: A Review

Given the recent popularity of FPGAs in performance-critical applications, power has become a top-level design constraint. While flexibility, parallelism and shorter time-to-market of FPGAs are attractive characteristics, they consume much higher power than comparable ASIC solutions making accurate early-stage power evaluation necessary. In this paper, reviews on power model and estimation in FPGA implementation are addressed with special focus on system level power estimation. Different power estimation techniques known from literature like probabilistic, statistical, simulation-based, and analytical methods were explored at various levels of abstraction. The work focuses on RTL-level and IP-based modeling techniques, regression and machine learning-based iterations, and their capacity to model dynamic power consumption. The review highlights the drawbacks of current system-level power estimation techniques, specifically their failure to accurately account for interconnection effects and power reduction in multi-IP systems. The findings indicate that while individual IP power models have achieved high accuracy, system-level estimation remains an open research challenge.