System Level FPGA Power Estimation: Evaluation and Analysis of Existing Models

Field Programmable Gate Arrays (FPGAs) are increasingly used as the platforms of choice for both modern embedded and high-performance computing. Nevertheless, the estimation of the local power consumption at the system level remains a difficult problem, especially in the case of multiple IP cores. This paper reviews the existing FPGA power estimation methods and their application to different architectures. In particular, the evaluation of system-level power estimation models for cascaded and non-cascaded architectures is highlighted. Experimental results show that conventional IP-summation models can achieve acceptable accuracy for non-cascaded systems but incur large estimation errors for cascaded systems as a result of the propagation of switching activity between IP cores. Therefore, this paper presents a modified estimation identity, which takes into account the effect of intermediate IP cores in cascaded architectures. This paper shows that architectural dependencies can have a large impact on the accuracy of power estimation. In addition, this work highlights gaps of the current approaches in research, especially the lack of integrated frameworks that combine IP-level modeling, system-level scalability, and runtime power optimization techniques. The results provide guidance towards accurate and scalable FPGA power estimation approaches for complex heterogeneous systems.