Performance Investigation of Digital Adders for Vedic Multiplier Design

The performance investigation of various digital adder architectures has been proposed for Vedic multiplier design. In this article, six different adder designs—the Carry Look-Ahead Adder, Han-Carlson Adder, Ripple Carry Adder, Carry Select Adder, Kogge-Stone Adder, Carry Save Adder, as well as a Compressor Adder, are systematically compared with respect to area, dynamic power loss, as well as propagation delay with the Power-Delay Product (PDP). The Cadence design environment is used to implement numerous adder architectures for a 16x16 Urdhva Tiryakbhyam (UT) Vedic multiplier. The synthesis results show that the compressor addition is the most suitable choice to achieve an optimized Urdhva Tiryakbhyam Vedic multiplier. As compared with typical adder architectures, the compressor adder achieved lower hardware area as well as delay. The results of this article are useful to finding out the best and most effective adder topologies for implementing UT Vedic multipliers.