Review on AI-Driven Automation for Efficient VLSI Physical Design and Optimization

The relentless scaling of CMOS technology has driven Very Large-Scale Integration (VLSI) circuits to unprecedented complexity, making traditional heuristic-based physical design flows increasingly inadequate. This literature review surveys recent advances in AI- and machine learning (ML)-driven automation spanning all major stages of the VLSI physical design flow — floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and sign-off. Key techniques including deep reinforcement learning (DRL), graph neural networks (GNNs), convolutional neural networks (CNNs), and transformer-based models are evaluated in terms of their impact on Power, Performance, and Area (PPA) metrics. Landmark contributions such as Google's AlphaChip, NVIDIA's AutoDMP, and Synopsys DSO.ai are discussed alongside open-source academic frameworks. The review also identifies current challenges — data scarcity, model interpretability, and scalability — and highlights future directions for autonomous, AI-native EDA flows.