Low Power Estimation Framework at System Level for FPGAs

Field Programmable Gate Arrays (FPGAs) are widely adopted in designing high performance and low power embedded systems. However, the power estimation at the system level remains a difficult problem, especially in the case of multiple IP cores. The system-level power estimation models for cascaded and non-cascaded architectures are available in literature. However, the available models are only experimented on conventional designs of moderate and high complexity level circuits that does not incorporate any low power technique. The battery-operated mobile systems need low power designs in order to reduce the battery life. Therefore, this paper presents some power reduction techniques at RTL level and an integrated frameworks that combine IP-level modeling, system-level scalability, and runtime power optimization techniques. The results provide guidance towards accurate and scalable FPGA power estimation approaches for complex heterogeneous systems targeted to low power designs.